Damascene-type interconnection structure and its production process

ABSTRACT

A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

FIELD OF THE INVENTION

[0001] The present invention relates to integrated circuits, and, moreparticularly, to a damascene-type interconnection structure.

BACKGROUND OF THE INVENTION

[0002] The interconnection structures of integrated circuits typicallyinclude aluminum doped with copper (Al—Cu), where the doping level isapproximately 2 to 4%. The process used for producing theseinterconnection structures includes depositing the metal, etching themetal to form the interconnection network, and depositing a dielectricthereon for insulating the metal lines both laterally (interlineinsulation) and vertically (interlevel insulation). This process iscommonly involves filling the interline spaces with the dielectric.

[0003] In order to improve performance characteristics (e.g., increasedspeed, lower consumption) it is necessary to use more conductive metalsand lower permittivity materials. For metallization purposes, copper(which has a resistivity roughly two times lower than Al—Cu) proves tobe a good candidate. Yet, the use of copper may be problematic in aconventional structure because it is very difficult to etch. This is whycopper is used in a so-called damascene structure. In a damascenestructure, the network of interconnections is formed by etching trenchesin a very low permittivity dielectric, depositing a metal nitridebarrier layer, and filling the trenches with copper. The excess copperand barrier material are then eliminated by polishing to leave only thedielectric between the metal lines. The production of such a structurerequires the use of dielectric material interface layers with hardmasks, and copper diffusion barrier or stop layers for mechanochemicalpolishing (CMP).

[0004] Dielectric interface materials such as SiO₂, Si₃N₄ andSiO_(x)N_(y) are conveniently used in damascene structures because theyare widely used in the production of integrated circuits. They may beused either in an active zone of the circuits as insulators or at theinterconnection level as intermetallic dielectrics or passivationdielectrics. These materials may be deposited by various well knownmethods, e.g. by thermal oxide growth, low pressure chemical vapordeposition CVD (LPCVD), atmospheric CVD (APCVD), or plasma assisted CVD(PECVD), as will be appreciated by those of skill in the art.

[0005] The required properties for dielectric interface materials indamascene structures are as follows. The materials used for the barriermust have a good resistance to the diffusion of copper. The materialsused as a hard mask must have good etching selectivity with respect tothe underlying materials of the organic or mineral type. Additionally,the materials used as a barrier layer to polishing must have a goodresistance to chemo-mechanical polishing in order to permit theelimination of the excess copper above the lines without deteriorationof the dielectric. In other words, these materials must have a highpolishing selectivity with respect to copper. Furthermore, thesematerials must also have good electrical strength characteristics,namely a low dielectric constant and low leakage current. Also, thematerials deposited directly on the very low permittivity dielectrics(i.e., the materials of the hard masks and barrier layers) must havegood chemical compatibility with these dielectrics.

[0006] Among the conventional dielectric interface materials, SiO₂ hasgood electrical properties and a good etching selectivity with respectto organic materials. Even so, its properties are inadequate in otherrespects. Si₃N₄ has a good etching selectivity, a good abrasionresistance, and a good resistance to the diffusion of copper, but itsdielectric constant is high. SiON provides intermediate characteristicsbetween those of Si₃N₄ and SiO₂. Thus, none of these conventionalmaterials exhibits all the desired properties.

[0007] In addition, certain of these dielectric interface materialsdeposited by PECVD, for example, from oxidizing gases (e.g., O₂, N₂O,NO₂, O₃ ) can induce an oxidation of the interface or the entire matrixof the low permittivity material. As a result, properties such asdielectric constant, leakage current, densification with thicknessmodification, adhesion loss and chemical modification may deteriorate.Dielectric materials with a very low permittivity based on Si—O, aporous structure, and having carbon radicals (of the Si—R type) orhydrides (of the Si—H type) are particularly affected by thesedeteriorations. Thus, for such materials, during the deposition of thedielectric interface material layer there is an oxidation of a depthvarying as a function of the porosity thereof. This oxidation inducesthe formation of silanol (Si—OH) and water, which are respectively verypolar radicals or molecules.

[0008] Accordingly, finding dielectric materials for use in producinginterface layers that satisfy the above-noted properties is problematic.

SUMMARY OF THE INVENTION

[0009] The invention makes it possible to produce structures of thedamascene type using dielectrics having a very low permittivity of theSi—O based mineral type having a porous structure. These very lowpermittivity dielectrics incorporate organic radicals (e.g. Si—CH₃) orhydrides (e.g. Si—H). The dielectrics may be xerogels, aerogels ofmethyl or silsesquioxane hydrogen, or any other material based on aporous mineral oxide which can incorporate organic radicals obtained bythe spreading of a precursor or by a CVD process. The dielectricinterface layers are formed by a combination of SiOCH and SiCH layers orsublayers.

[0010] According to the invention, a method for making a damascene-typeinterconnection structure adjacent a surface of a microelectronic deviceincludes depositing a first dielectric material layer adjacent thesurface and depositing a first dielectric material interface layer onthe dielectric material layer. The first dielectric material interfacelayer is deposited by depositing a first SiCH layer on the dielectriclayer and depositing a first SiOCH layer on the SiCH layer. At least oneinterconnection is formed within the first dielectric material layer tocontact the surface, and the first dielectric material layer provides ahousing for the at least one interconnection.

[0011] The first dielectric material layer may include a very lowpermittivity dielectric material of a mineral type based on Si—O andhaving at least one of an organic radical or a hydride. The method mayalso include depositing a second dielectric material layer on the firstdielectric material interface layer and depositing a second dielectricmaterial interface layer on the second dielectric layer. The seconddielectric material interface layer may be deposited by depositing asecond SiCH layer on the second dielectric material layer and depositinga second SiOCH layer on the second SiCH layer. Depositing the seconddielectric material interface layer may also include depositing a thirdSiCH layer on the second SiOCH layer.

[0012] Forming the at least one interconnection may include forming atleast one copper interconnection, and a metal layer may be depositedadjacent the first dielectric material layer prior to forming the atleast one copper interconnection to reduce diffusion of copper into thefirst dielectric material layer. The microelectronic device may beformed on a silicon substrate, for example. Furthermore, forming the atleast one interconnection may include etching at least one hole in thefirst SiOCH layer, etching portions of the first SiCH layer, the firstdielectric material interface layer, and the first dielectric materiallayer beneath the at least one hole using the first SiOCH layer as anetching mask to thereby form at least one trench. Copper may then bedeposited within the at least one trench to thereby form the at leastone interconnection. A barrier layer may be deposited in the trenchprior to depositing the copper to reduce diffusion of the copper intothe first dielectric material layer.

[0013] According to an alternative embodiment, a method for making adual damascene-type interconnection structure on a surface of asemiconductor substrate to provide at least one interconnection with atleast one conductive line formed in the semiconductor substrate is alsoprovided. The method may include depositing a first dielectric materiallayer having a very low permittivity on the surface and depositing afirst interface layer on the first dielectric material layer. At leastone hole may be etched in the first interface layer to expose at leastone portion of the first dielectric material layer. A second dielectricmaterial layer having a very low permittivity may be deposited on thefirst interface layer and the at least one exposed portion of the firstdielectric material layer.

[0014] A second interface layer may be deposited on the seconddielectric material layer, and at least one hole may be etched in thesecond interface layer and the first dielectric material layertherebeneath to thereby form at least one trench exposing the at leastone copper line. The first and second interface layers thereby providehard masks for etching the first and second dielectric material layers.Also, a layer of a first metal may be deposited in the trench, and asecond metal may be deposited thereon to form the interconnection withthe at least one copper line. The layer of the first metal reducesdiffusion of the second metal into the first and second dielectricmaterial layers and the first and second interface layers. The first andsecond dielectric material layers thus form a housing for the at leastone interconnection.

[0015] The at least one conductive line may include the second metal,and a barrier layer may be deposited on the substrate prior todepositing the first dielectric material layer to prevent diffusion ofthe second metal from the at least one conductive line into the firstdielectric material layer. Depositing the first interface layer mayinclude depositing an SiCH layer on the dielectric material layer anddepositing an SiOCH layer on the SICH layer. Additionally, etching theat least one hole in the first interface layer may include depositing aresin mask on the SiOCH layer, etching at least one hole in the SiOCHlayer using the resin mask to expose at least one portion of the SiCHlayer, removing the resin mask, and etching the at least one exposedportion of the SiCH layer to the thereby expose the at least one portionof the first dielectric material layer.

[0016] Depositing the second interface layer may include depositing afirst SiCH layer on the second dielectric material layer, depositing anSiOCH layer on the SiCH layer, and depositing a second SiCH layer on theSiOCH layer. Etching the at least one hole in the second interface layerand the first dielectric material layer therebeneath may includedepositing a resin mask adjacent the second SiCH layer, etching at leastone hole in the second SiCH layer using the resin mask to expose atleast one portion of the SiOCH layer, removing the resin mask, andetching the at least one exposed portion of the second SiOCH layer andcorresponding portions of the first SiCH layer, the second dielectricmaterial layer, and the first dielectric material layer therebeneath tothereby form the at least one trench. Furthermore, the third SiCH layermay be removed after completing the etching steps.

[0017] The method may further include polishing the second interfacelayer after depositing the layer of the first metal layer and depositingthe second metal to thereby remove any excess metal therefrom. Also, theconductive line and the second metal may include copper.

[0018] A damascene-type interconnection structure according to thepresent invention on a surface of a microelectronic device includes afirst dielectric material layer on the surface and a first dielectricmaterial interface layer on the first dielectric material layer. Thefirst dielectric material interface layer may include a first SiCH layeron the first dielectric layer and a first SiOCH layer on the first SiOCHlayer. The interconnection structure also includes at least oneinterconnection within the first dielectric material and in contact withthe surface of the microelectronic device.

[0019] The first dielectric material layer may include a very lowpermittivity dielectric material of a mineral type based on Si—O andhaving at least one of an organic radical or a hydride. A seconddielectric material layer may be included on the first dielectricmaterial interface which includes a second SiCH layer on the firstdielectric material interface layer and a second SiOCH layer on thesecond SiCH layer. The microelectronic device may be formed on a siliconsubstrate, and the at least one interconnection may include copper.Furthermore, a barrier may be included between the surface and the firstdielectric material layer to reduce diffusion of copper from the atleast one interconnection into the first dielectric material layer.

[0020] A dual damascene-type interconnection structure according toanother embodiment of the present invention is also provided. The dualdamascene-type interconnection structure is on a surface of amicroelectronic device formed on a silicon substrate, and the surfaceincludes at least one copper line for connection to the interconnectionstructure. The double damascene-type interconnection structure mayinclude a first barrier layer on the surface to reduce diffusion ofcopper from the at least one copper line and a first dielectric materiallayer having a very low permittivity on the barrier layer. Furthermore,a first interface layer is included on the first dielectric materiallayer including a first SiCH layer on the first dielectric materiallayer and a first SiOCH layer on the first SiCH layer. A seconddielectric material layer having a very high permittivity may beincluded on the first interface layer. A second interface layer on thesecond dielectric material layer may include a second SiCH layer on thesecond dielectric material layer and a second SiOCH layer on the secondSiCH layer. At least one copper interconnection may be included withinthe structure and electrically connected to the at least one copperline. Also, a second barrier layer separating the at least one copperinterconnection and the first and second dielectric material layers maybe included to prevent diffusion of copper therein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The invention will be better understood and other advantages andfeatures will become apparent from the following description andaccompanying drawings, which are given by way of non-limiting example,in which FIGS. 1 through 10 are cross-sectional views illustrating themaking of a dual damascene-type interconnection structure according tothe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] As noted above, the combination of SIOCH and SICH layer orsublayers according to the present invention provides the desiredqualities for producing a good interface layer. The following tablecompares SiCH and SiOCH with other dielectric materials currently usedin microelectronics. The symbols + and − and their number respectivelyindicate the more or less satisfactory properties. The last line in thetable relates to the chemical compatibility between each material in thetable and the dielectric materials for housing the interconnections.Materials Properties SiO₂ Si₃N₄ SiON SiCH SiOCH Dielectric constant 4.38 6.5 5.5 2.7 Fluorine/SiO₂ etching 0   ++ + +++ + selectivityResistance to abrasion/Cu + ++ + +++ ++ Cu diffusion − ++ − +++ −Chemical compatibility −−− + − + −−

[0023] The above table illustrates that SiCH and SiOCH together havequalities which are desirable for producing a good interface layer,i.e., resistance to abrasion and copper diffusion, etching selectivityfor SiCH, and a low dielectric constant for SiOCH. In addition, SiCH isproduced without any oxidizing precursor. These two materials have agood mutual compatibility and can be deposited in the same reactor fromequivalent precursors of the methyl, dimethyl, trimethyl or phenylsilane types. SiOCH is obtained by adding an oxidizing precursor of theO₂, N₂O, NO₂ or CO₂ type.

[0024] An example of the production of a double damascene structure willbe now be described with reference to FIGS. 1 through 10, which arepartial, cross-sectional views of a double damascene interconnectionstructure according to the present invention. As seen in FIG. 1, acopper line 1 is flush with a surface 2 of a dielectric 3 deposited on asemiconductor substrate (not shown). An interface layer 4 is depositedon the surface 2 and serves as a barrier layer to the diffusion ofcopper. The thickness of the layer 4 may be between 10 and 30 nm, forexample. A very low permittivity dielectric material layer 5 known as adielectric via is then deposited on the layer 4 and has a thicknessbetween 0.5 and 1 um, for example, as seen in FIG. 2.

[0025] An interface layer 10 is then deposited on the dielectricmaterial layer 5, as shown in FIG. 3. The interface layer 10 is used forforming a hard mask and includes a SiCH sublayer 11 deposited on thedielectric material layer 5 and a SiOCH sublayer 12 deposited on theSiCH sublayer 11. The sublayer 11 may have a thickness in a range ofabout 10 and 20 nm, whereas the thickness of the sublayer 12 may beabout 100 nm, for example. This sublayer stack is compatible with thelow permittivity material of the layer 5 because SiCH does not oxidizethe dielectric and ensures an excellent etching selectivity. That is, itprovides a hard mask/low permittivity dielectric.

[0026] In order to subsequently permit an electrical connection with theline, a photosensitive resin layer 20 is deposited on the interfacelayer or hard mask 10 and an etching hole 21 is defined therein over theline 1. The etching of the hard mask 10 takes place in three steps.First, a hole is etched in the SIOCH sublayer 1 until the SICH sublayer11 is revealed. The resin layer 20 is then removed and the dielectricvia layer 5, which is very sensitive to the oxidation produced by theresin removal oxidizing agents (O₂ plasma, organic bases, etc.), isprotected by the sublayer 11, as seen in FIG. 4. Finally, the sublayer11 is etched using the sublayer 12 as a mask.

[0027] As may be seen in FIG. 5, a very low permittivity dielectricmaterial layer 6 called the “line dielectric” is deposited on theinterface layer 10 and fills the hole made in the layer 10. Thethickness of the layer 6 may be in a range of about 0.3 to 0.6 μm, forexample. An interface layer 30 is then deposited on the dielectricmaterial layer 6, as shown in FIG. 6. The interface layer 30 includesthree sublayers, namely (in the order of deposition): a SiCH sublayer 31having a thickness below about 10 nm, for example, and compatible withthe dielectric material of the layer 6; a SiOCH sublayer 32 having athickness in a range of about 100 and 150 nm, for example; and a SiCHsublayer 33 preferably having a thickness slightly greater than the sumof the thicknesses of layer 2 and SiCH sublayer 31.

[0028] The interface layer 30 serves as a stop or barrier layer to achemo-mechanical polishing (CMP) and also as a hard mask. The sublayer31 serves to reduce the oxidation of the dielectric layer 6. Sublayer 32acts as a polishing stop layer, i.e., it protects the dielectric layer 6from polishing uniformity defects. Furthermore, the sublayer 32 limitsthe effects of copper removal during the CMP step. The sublayer 33serves as an etching countermask making it possible to etch in a singlestep a hole revealing the line 1.

[0029] As shown in FIG. 7, a photosensitive resin layer 40 is depositedon the interface layer 30, and an etching hole 41 is defined thereinabove the hole previously etched in the hard mask 10. A hole is firstetched in the SiCH sublayer 33 with the SiOCH sublayer 32 serving as astop or barrier. The resin is then removed and the dielectric materialof layer 6 is protected by the sublayers 31 and 32. The etching of thehard mask 30 continues until the line dielectric layer 6 is revealed, asshown in FIG. 8. The SiCH sublayer 33 is etched over its entire surfaceto a thickness which is preferably at least equivalent to the thicknessof the SiCH sublayer 31.

[0030] The low permittivity dielectric material of the layers 5 and 6 isthen etched through the holes made in the hard masks 10 and 30 until theSiCH layer 4, which serves as a copper diffusion barrier layer, isreached. The remainder of the SiCH sublayer 33 and the SiCH layer 4 atthe bottom of the etched hole or trench 7 are then simultaneously etchedand the line 1 is revealed, as shown in FIG. 9.

[0031] A titanium nitride or tantalum nitride layer 8 is uniformlydeposited on the structure and serves as a metal diffusion barrier, asseen in FIG. 10. This layer also adheres to the walls and bottom of thehole 7, which is then filled with copper. The excess metal barrier andcopper are then polished using the SiOCH sublayer 32 as a stop orbarrier. A copper connection 9 is thus exposed traversing the viadielectric layer 5 and the line dielectric layer 6 to make contact withthe line 1.

[0032] The following example will illustrate the advantages of thestructure according to the invention. For a layer 6 (line dielectric)having a thickness of about 0.4 um and a dielectric constant of about 2,an SiCH barrier sublayer 31 having a thickness of about 5 nm, and anSiOCH sublayer 32 having a thickness of about 50 nm, the dielectricconstant equivalent for this stack is about 2.25. By way of comparison,the use of SiN in place of SiCH and the use of SiO₂ in place of SiOCHwould lead to an equivalent dielectric constant of about 2.55.

That which is claimed is:
 1. Process for the production of adamascene-type interconnection structure on a face (2) to be connectedof a microelectronic device, comprising the deposition of at least onedielectric material layer (5, 6) on said face (2) to be connected andwhich is to house said interconnections (9), the process also comprisingthe deposition of at least one dielectric material interface layer (10,30) in intimate contact with said dielectric material layer (5, 6) forhousing the interconnections (9), characterized in that said interfacelayer (10, 30) is formed by the deposition of at least one SiOCHsublayer (12, 32) and at least one SiCH sublayer (11, 31, 33). 2.Process according to claim 1 , characterized in that the deposition of adielectric material layer (5, 6) for housing the interconnections (9)consists of depositing a layer of a material chosen from among very lowpermittivity dielectric materials of the mineral type based on Si—O,having organic radicals or hydrides.
 3. Process according to one of theclaims 1 or 2, characterized in that the interface layer (10, 30)comprises a SiCH sublayer (11, 31) deposited on and in contact with thedielectric material layer (5, 6) for housing the interconnections (9), aSiOCH sublayer (12, 32) being deposited on and in contact with the SiCHsublayer (11, 31).
 4. Process according to any one of the claims 1 to 3, characterized in that the microelectronic device is produced onsilicon (3).
 5. Process according to any one of the claims 1 to 4 ,characterized in that with the interconnections (9) made from copper,deposition takes place of a metal layer (8) forming a barrier to thediffusion of copper into the dielectric material layer (5, 6) forhousing the interconnections.
 6. Process according to claim 3 ,characterized in that the SiOCH sublayer (12)′ is used as the etchingmask for the SiCH sublayer (11) for housing the interconnections (9) inthe corresponding dielectric material layer.
 7. Process for theproduction of a double damascene-type interconnection structure on aface (2) having copper conductive lines (1) to be connected,characterized in that it comprises the following steps: deposition onthe face (2) to be connected of a barrier layer (4) to the diffusion ofcopper into SiCH, deposition on the barrier layer (4) of a first verylow permittivity dielectric material layer (5) for housing saidinterconnections, deposition on a first interface layer (10) on saidfirst dielectric material layer (5), comprising a SiCH sublayer (11)deposited on an din contact with the first dielectric material layer anda SiOCH sublayer (12), etching holes in said SiOCH sublayer (12) facingthe conductive lines (1) to be connected by means of a resin mask (20)until the SiCH sublayer (11) is revealed, removal of the resin mask(20), etching that part of the SICH sublayer (11) which has beenrevealed until the first dielectric material layer (5) is reached,deposition on the first etched interface layer (10) of a second very lowpermittivity dielectric material layer (6) for the housing of saidinterconnections, deposition of a second interface layer (30) on saidsecond dielectric material layer (6), successively comprising a firstSiCH sublayer (31) deposited on and in contact with the seconddielectric material layer (6), a second SiOCH sublayer (32) and a thirdSiCH sublayer (33), etching holes in said third sublayer (33) facing theconductive lines (1) to be connected by means of a resin mask (40) untilthe second sublayer (32) is revealed, removal of the resin mask (40),etching that part of the second sublayer (32) which has been revealedand that part of the first sublayer (31) revealed by the etching of thesecond sublayer (32), etching holes (7) through the second dielectricmaterial layer (6), the first dielectric material layer (5) and thebarrier layer (4), said interface layers (30, 10) serving as a hardmask, up to the revealing of the conductive lines (1), said thirdsublayer (33) also being eliminated, uniform deposition of a metal layer(8) serving as a barrier to the diffusion of copper onto the stack ofetched layers, deposition of a copper layer filling the holes (7) etchedin the structure, polishing the excess copper and metal layer (8)covering the second sublayer (32) for revealing the second sublayer (32)and supplying the interconnections (9).
 8. Damascene-typeinterconnection structure on one face of a micro-electronic device,comprising at least one dielectric material layer (5, 6) for housingsaid interconnections (9) and at least one dielectric material interfacelayer (10) in intimate contact with said dielectric material layer forhousing the interconnections, characterized in that said interface layer(10) comprises at least one SiOCH sublayer (12) and at least one SiCHsublayer (11).
 9. Interconnection structure according to claim 8 ,characterized in that the dielectric material layer (5, 6) for housingsaid interconnections (9) is a layer of a material chosen from amongvery low permittivity dielectric materials of the mineral type based onSi—O and having organic radicals or hydrides.
 10. Interconnectionstructure according to one of the claims 8 or 9, characterized in thatthe interface layer (10) comprises a SiCH sublayer (11) on and incontact with the dielectric material layer (5) for housing theinterconnections, a SiOCH sublayer (12) being deposited on and incontact with the SiCH sublayer (11).
 11. Interconnection structureaccording to any one of the claims 8 to 10 , characterized in that themicroelectronic device is a device produced on silicon (3). 12.Interconnection structure according to any one of the claims 8 to 11 ,characterized in that the interconnections (9) are of copper, thestructure comprising a metal layer (8) forming a barrier to thediffusion of copper into the dielectric material layer (5, 6) forhousing the interconnections (9).
 13. Double damascene-typeinterconnection structure on a face (2) to be connected of amicroelectronic device produces on silicon, said face (2) having copperconductive lines (1) to be connected, characterized in that itcomprises: a barrier layer (4) to the diffusion of copper into the SiCHdeposited on said face (2), a first very low permittivity dielectricmaterial layer (5) deposited on the barrier layer (4), a first interfacelayer (10) deposited on said first dielectric material layer (5),comprising a SiCH sublayer (11) deposited on and in contact with thefirst dielectric material layer (5) and a SiOCH sublayer (12), a secondvery high permittivity dielectric a material layer (6) deposited on thefirst interface layer (10), a second interface layer (30) deposited onthe second dielectric material layer (6) and comprising a first SiCHsublayer (31) deposited on and in contact with the second dielectricmaterial layer (6) and a second SiOCH sublayer (32), copperinterconnections (9) traversing said structure for establishingelectrical connections with said conductive lines (1), a barrier layerto the diffusion of copper (8) separating the interconnections (9) fromthe very low permittivity dielectric materials layers (5, 6).